Inside IBM's path to Starling: what the November 2026 error-correction results show, and what they don't

The goal: 200 logical qubits and 100 million operations

IBM says IBM Quantum's Starling system, planned for 2029, will run circuits of 100 million quantum operations on 200 logical qubits. A logical qubit is one unit of protected quantum information spread across many physical qubits, so that errors can be detected and corrected faster than they build up. Our error-correction explainer covers the basics.

Starling's design rests on a family of quantum low-density parity-check (qLDPC) codes called bivariate bicycle codes, which IBM researchers published in Nature in 2024. Their headline example, the [[144,12,12]] "gross" code, stores 12 logical qubits in 288 physical qubits. The paper estimates that the widely used surface code would need nearly 3,000 physical qubits for comparable protection, assuming a physical error rate of 0.1%. In 2025 IBM described how to build a full computer from such codes, the "bicycle architecture": code modules, each with a logical processing unit, joined by adapters and fed by magic-state factories.

The catch is wiring. In the original scheme, each qubit must talk to six others, and some of those partners sit far away on the chip. That is why the November 2026 results focus on couplers, links and fabrication rather than on qubit counts.

What IBM reported on November 11

IBM published the update alongside its Quantum Developer Conference, the same day as the Nighthawk r3 roadmap we covered separately. The table sets each reported result against the target IBM gives for Starling. All figures are IBM's own.

Building block	Reported in November 2026	Starling requirement or status
Physical qubits (Loon chip)	Coherence time (T1) of about 200 µs; median gate error near 0.3%	T1 in the millisecond range; gate errors in the low 0.01% range
Best gates on current chips	Heron and Nighthawk gate errors as low as 0.04%	Low 0.01% range
On-chip long-range couplers (c-couplers)	Resonator quality factor above 10 million; three wiring layers instead of two; 20 mm length	IBM says these exceed what Starling needs
Error-correcting code	Revised code needs five connections per qubit instead of six; IBM reports 20x to 100x lower logical error rates	Simulated, not yet run on hardware
Fabrication	Josephson junctions per processor cut from about 5,000 to about 2,000	More chips with every junction working
Decoder	Relay-BP algorithm extended; dedicated chip on a 2 nm process in development	IBM says the algorithm already meets Starling's needs
Chip-to-chip links (l-couplers)	Four links between two Nighthawk chips; about 1% average error (best 0.7%)	More than 100 links per module at 0.1% error
Cryogenics	Two modular cryostats joined, cooled below 15 mK in under five days	Up to 12 cryogenic modules
Control electronics	Cryogenic control chips now match or beat room-temperature gate performance	Scaling path for wiring inside the fridge

Why fewer junctions matter more than it sounds

One of the least flashy items may be the most practical. IBM says its revised code lets each processor use about 2,000 Josephson junctions instead of about 5,000. At a 99.95% yield per junction, IBM estimates that one processor in three would come out fully working, compared with one in twelve before.

The arithmetic checks out. If every junction must work, the odds of a perfect chip are 0.9995 raised to the number of junctions. That gives roughly 8% for 5,000 junctions and roughly 37% for 2,000, a gain of more than four times. For a machine that needs many identical modules, yield is a cost and schedule problem as much as a physics one.

The weakest link is literally the link

Starling is modular: processors in separate chips and separate cryostats must exchange quantum states. IBM's l-coupler results are the clearest measure of how far that has come. In a separate technical post (see our earlier report), IBM reports linking two Nighthawk processors with four l-couplers over 80 cm aluminium coaxial cables. State transfer across the links averaged 99%, with a best of 99.3%. A two-qubit gate performed between the chips averaged 94.75% fidelity across the four links, well below on-chip gates.

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There is a small discrepancy worth noting. IBM's written materials give 99.3% as the best link result, while Ars Technica quotes IBM's Oliver Dial at up to 99.4 percent. Either way, IBM's own target for Starling is a 0.1% link error, roughly ten times better than today's average. Starling also needs more than 100 such links per module, against four in this demonstration.

The rollout of linked chips has also slowed. IBM's March 2026 roadmap expected up to three linked 120-qubit Nighthawk modules (360 qubits) in 2026. Ars Technica reports that the plan has been cut from nine linked chips to two, and the first two-chip system, built from 520-qubit Nighthawk r3 processors, is now slated for 2027.

Decoding: a claim to read carefully

Error correction only works if a classical decoder can work out which errors happened, in real time, from the stream of measurements. IBM's Relay-BP decoder, described in a 2025 preprint, is a lightweight message-passing method designed to run on FPGAs or custom chips. In simulation it outperformed a standard decoder (BP+OSD) on bivariate bicycle codes. The preprint estimates a budget of roughly 600 iterations to decode a 12-cycle circuit at one microsecond per cycle.

IBM now says Relay-BP already meets Starling's requirements and that it is designing a dedicated decoder chip on a 2 nm process. That is a strong claim about an algorithm, but it rests on simulations. A decoder keeping up with a live logical memory on real hardware is a separate milestone. IBM's March roadmap promised a decoder prototype in 2026, and the November materials describe the chip as still in development.

A different scaling bet

Not every superconducting-qubit company is taking the same route. On November 10, Rigetti Computing reported a 99.5% median two-qubit gate fidelity on its 108-qubit Cepheus system, which is built from twelve nine-qubit chiplets. Rigetti says it plans to scale by packing more qubits into a single dilution refrigerator rather than networking refrigerators together. IBM is betting on linked cryostats. Both strategies are company-reported, and neither has yet shown error-corrected computation at scale.

Hype versus substance

• Substance: IBM is publishing component-level numbers with explicit targets, which makes progress measurable. The c-coupler quality factors, the junction-yield arithmetic and the cryostat integration are concrete engineering steps.
• Not yet shown: the November materials we reviewed do not report a qLDPC logical memory running on Loon-class hardware with real-time decoding. IBM's roadmap says a processor called Kookaburra will demonstrate one Starling module (a logical processing unit plus memory); that demonstration was not reported as complete.
• Gaps are large: Loon's median gate error (about 0.3%) is more than ten times the Starling target, and link error is about ten times too high, across 25 times fewer links than one module needs.
• Model-based savings: the claim that Starling needs roughly ten times fewer physical qubits than other fault-tolerant designs depends on noise models such as the 0.1% physical error rate used in the 2024 paper.
• Self-reported: most of these figures come from IBM blog posts and press materials, not peer-reviewed papers. Treat them as the company's account until independent results appear.

What to watch

Four signals will show whether the 2029 date is holding: a hardware demonstration of a bivariate bicycle logical memory with real-time decoding; l-coupler error falling toward 0.1% as link counts rise; delivery of the two-chip Nighthawk r3 system in 2027; and the US Department of Energy's Genesis Mission goal, cited by IBM, of 100 logical qubits running 100,000 hard operations by late 2028. For how to weigh claims like these, see our guide to reading a quantum computing announcement.